In-System Programming—IP2022 User’s Manual 360 www.ubicom.com Before   programming   the   flash   memory   through   the   ISD/ISP
interface, the OSC clock must be running and the CPU must be
stopped (i.e. break mode). The debugger/programmer can read
the  FUSE0  and  FREQ  registers  in  the  configuration  block  to
determine the flash timing parameters, which are then loaded in
the  flash  configuration  (FCFG)  register.  If  the  CPU  clock  is  not
running  or  the  settings  in  the  FUSE0  or  FREQ  registers  are
incorrect, the IP2022 may fail to program. Programming each word takes about 30–40 microseconds. The
SPI  bus  transferring  three-byte  commands  at  1  MHz  takes  a
minimum of 24 clock cycles per command, or 24 microseconds.
Therefore, the speed of programming at this clock rate is limited
by the flash write speed, not the speed of the SPI bus. After programming, the contents of the flash memory should be
verified using IREAD commands (again, not to be confused with
the   iread   instruction),   which   automatically   increment   the
address pointer. To read the same flash location multiple times,
the  address  pointer  must  be  reinitialized  using  ADDR_HI  and
ADDR_LO commands between IREAD commands. For   gang   programming,   multiple   processor   chips   could   be
connected as shown in Figure 6-2. The programmer must verify
that  all  chips  are  done  for  a  given  program  command  before
proceeding by checking their command acknowledge signal (i.e.
the DONE bit). This configuration also allows the programmer to
individually verify the programming of each chip.