IP2022 User’s Manual—In-System Debugging
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355
Table 5-4 ISD/ISP Timing Specifications
Symbol
Parameter
Min
Typ
Max Units
t1
TSS select asserted to TSO
driven
5
ns
t2
Clock period
50
ns
t3
Clock high time
20
ns
t4
Clock low time
20
ns
t5
TSI data setup time before TCLK
positive edge
5
ns
t6
TSI data hold time after TCLK
positive edge
5
ns
t7
TSO hold time after negative edge
of TCLK
5
ns
t8
TSS negated to TSO undriven
5
ns
t9
Last falling edge of TSCK to TSS
negated
20
ns
t10
Negation time between Multiple
Transfer Cycles
100
ns
