IP2022 User’s Manual—In-System Debugging www.ubicom.com 351 • TSCK (Target Serial Clock)—Clock input used to synchronize
data transfer through the TSI and TSO signals. • TSS  (Target  Slave  Select)—Active-low  select  signal  which,
when asserted, enables the IP2022 to communicate on the
SPI bus. This signal must be asserted before data transfers
and  must  stay  low  for  the  duration  of  the  transaction.  The
transaction is defined as an 8-bit transfer, and with the clock
phase and polarity options chosen provides the flexibility of
keeping TSS asserted or negated between transactions. • TSI  (Target  Serial  Input)—Sampled  on  the  rising  edge  of
TSCK. Unidirectional input signal to the processor driven by
the SPI master. • TSO (Target Serial Output)—Driven after the falling edge of
TSCK.  Unidirectional  output  signal  from  the  IP2022  driven
only when the processor SPI interface is selected by asserting
TSS. Placed in high-impedance mode if the IP2022 is not se-
lected. 5.5.1 Recommended Connector Pin Assignments The recommended connector layout for the ISD/ISP interface is
shown in Figure 5-8. The recommended connector is male 10-pin
connector with 100-mil pin spacing, whose pin assignments are
listed in Table 5-2. The connector is keyed to prevent backward
insertion.