IP2022 User’s Manual—System Architecture www.ubicom.com 19 W  or  Working  register—the  source  or  destination  for  most
arithmetic and logical instructions.
STATUS register—condition flags for the results of arithmetic
and logical operations, the page bits (used for jumps and sub-
routine calls), and bits which indicate the cause of the last re-
set (watchdog timer overflow or brown-out voltage detector).
Section 2.1.1 shows the assignment of the bits in the STATUS
register.
MULH register—receives the upper 8 bits of the 16-bit product
from signed or unsigned multiplication. The lower 8 bits are
loaded into the W register.
SPDREG  register—holds  bits  that  indicate  the  CPU  speed
and clock source settings loaded by the speed instruction, as
shown  in  Section  2.1.2.  For  more  information  about  the
speed  instruction  and  the  clock  throttling  mechanism,  see Section 2.4 INTSPD register—holds bits that control the CPU speed and
clock source during interrupt service routines. It has the same
format as the SPDREG register.
XCFG  register—holds  additional  control  and  status  bits,  as
shown in Section 2.1.3.
PCH/PCL register—16-bit program counter. IPCH/IPCL  register—specifies  the  return  address  when  a reti instruction is executed. On returning from the interrupt service routine, an option of the reti instruction allows soft-
ware to save the incremented value of the program counter in
the INTVECH and INTVECL registers.