In-System Debugging—IP2022 User’s Manual 330 www.ubicom.com The  clock  is  suspended  to  the  following  peripherals  in  Break
mode: • Real-Time Timer • Timer 0 • Timer 1 • Timer 2 • ADC Timer • Watchdog Timer (only if the ISD/ISP interface is open) The   timers   used   for   flash   memory   read,   write,   and   erase
operations continue to function in Break mode. If the Watchdog
Timer is enabled, it will be running after the ISD/ISP interface is
opened  until  the  DEBUG_RESET  command  is  issued.  If  the
Watchdog   Timer   overflows   during   this   interval,   the   start-up
sequence should be repeated. 5.2 ISD/ISP Interface Protocol The    ISD/ISP    interface    protocol    consists    of    transmitting    a
command   byte   followed   by   a   16-bit   operand   word   while
simultaneously receiving a command acknowledge byte (for the
previous command) followed by a 16-bit return value, as shown in
Figure 5-1. Command and command acknowledge formats have
a fixed length of three bytes. There are two types of commands:
commands that require a response such as the IREAD command
(read from program memory, not to be confused with the iread
instruction),  and  commands  that  do  not  require  any  data  to  be
returned. The SPI bus requires that the same number of bits are