IP2022 User’s Manual—In-System Debugging www.ubicom.com 329 The  CPU  core  clock  remains  unchanged  on  entry  into  Break
mode, except in the following cases: • An INITIALIZE or BREAK command was issued through the
ISD/ISP interface, and the system clock is off. • An INITIALIZE or BREAK command was issued through the
ISD/ISP interface, and the system clock is derived from RT-
CLK (rather than the OSC clock). • An INITIALIZE or BREAK command was issued through the
ISD/ISP interface, and the CPU core clock is off. In these cases, the CPU core clock is changed to the OSC clock
(i.e.  PLL  bypass)  with  a  clock  divisor  of  1.  This  change  is  not
reflected in the SPDREG register, which will continue to indicate
the speed before entry into Break mode. If a flash memory read, write, or erase operation is in progress, the
operation will continue in Break mode. The debugger must poll the
FBUSY bit to ensure the operation is complete before making any
change to the CPU core speed. If the debugger changes the CPU
core speed before exiting Break mode (by issuing a STEP or RUN
command), the speed must be restored to its value on entry into
Break mode. If the CPU core clock is off when Break mode is entered, the CPU
will execute one instruction before entering Break mode. There is
no mechanism through the ISD/ISP interface for returning to Run
mode with the CPU core clock shut off, because the STEP and
RUN commands cannot be issued unless the CPU core clock is
running.