Peripherals—IP2022 User’s Manual 326 www.ubicom.com EMBRT Enable bus release wait state 0 =    No wait state
1 =    One wait state added between a read cycle fol- lowed by a write cycle EMWRT2:0 WR pulse width, in CPU core clock cycles 000 =    1
001 =    2
010 =    3
011 =   4
100 =    5
101 =    6
110 =   7 111 =    8 EMRDT2:0 RD pulse width, in CPU core clock cycles 000 =    1
001 =    2
010 =    3
011 =   4
100 =    5
101 =    6
110 =   7 111 =    8 Name Description