IP2022 User’s Manual—Peripherals www.ubicom.com 323 Software   is   responsible   for   inserting   a   one-instruction   delay
between changing the address (i.e. the contents of the ADDRSEL,
ADDRX,   ADDRH,   or   ADDRL   registers)   and   executing   the iread/ireadi or iwrite/iwritei instruction, if required by the  timing  of  the  external  latch.  Table  4-15  shows  the  timing
specifications which the register must meet for operation without
delay insertion. For zero wait-state access, the external memory must meet the
access time specification shown in Table 4-16. Slower memories
can be accommodated by programming wait states in the EMCFG
register. Software is responsible for allowing the memory cycle to
complete before reading the DATAH/DATAL registers. Table 4-15  External Latch Timing Specifications Parameter Value (ns) Minimum LE pulse width 7 Setup time before LE falling edge 4 Hold time after LE falling edge 2 Input to output delay, transparent mode 15