IP2022 User’s Manual—Peripherals www.ubicom.com 319 is writing to the slave. Optionally, a HOLD signal may be enabled
as  an  alternate  function  of  port  pin  RB5.  Assertion  of  HOLD
indicates to the external master that the Parallel Slave Peripheral
interface is not ready to allow the data transfer to complete. The
HOLD signal should have an external pullup resistor (R1 = 10K W is recommended). The CS signal must not be allowed to float. Internally, an interrupt is generated when CS is asserted. Software
then reads the Port C, Port D, or both if the data transfer is a write
from the external master. If the data transfer is a read, software
writes the data to the port or ports. Finally, software releases the
HOLD  signal  (if  enabled)  by  writing  to  the  PSPRDY  bit  in  the
PSPCFG register. The  Parallel  Slave  Peripheral  does  not  generate  interrupts  by
itself. Software is required to enable port pin RB7 (the CS input)
as a falling-edge interrupt input for the Parallel Slave Peripheral to
function. The CS signal must go high, then back low, for each data
transfer. RB6 (the R/W input) must also be configured as an input.
The setting in the RBDIR register for RB5 (the HOLD output) is
overridden by the programming of the Parallel Slave Peripheral. The   PSPCFG   register   is   used   to   enable   the   Parallel   Slave
Peripheral, select which ports are used for data transfer, enable
the HOLD output, and release the HOLD output when the data
transfer is ready to complete.