Peripherals—IP2022 User’s Manual 316 www.ubicom.com used    to    enable    automatic    loading    from    SERDES2.    The
HL_TRIGGER  bit  in  the  LFSRCFG3  register  controls  whether
loading the DATAINH or DATAINL register triggers the start of the
LFSR   operation.   The   ML_IN   bit   in   the   LFSRCFG3   register
controls  whether  data  is  shifted  MSB-first  or  LSB-first  from  the
DATAIN register to the DIN node. 4.9.5 DATAOUT Register The    8-bit    DATAOUTH    and    DATAOUTL    registers    together
comprise  the  16-bit  DATAOUT  register.  Data  shifted  out  of  the
residue register is shifted LSB-first into the DATAOUT register. 4.9.6 DOUT Register The  DOUT  register  controls  a  40:1  multiplexer  on  the  residue
register outputs. It selects a term which can be used in the source
gating for the DOUT bit stream. 4.9.7 FBx Registers The  four  FBx  registers  control  four  40:1  multiplexers  on  the
residue register outputs. They select feedback terms which can be
used in the source gating for the D0, POLY_XOR_EN, and DOUT
bit streams.