Peripherals—IP2022 User’s Manual 308 www.ubicom.com in the RESCMP register are initialized to the same values as these
non-participating bits. Each  LFSR  unit  has  three  configuration  registers  (LFSRCFG1,
LFSRCFG2, and LFSRCFG3) for various control and status bits.
The HL_TRIGGER bit in the LFSRCFG3 register controls whether
operation of the LFSR unit is triggered by a write to the high byte
or the low byte of the DATAIN register (i.e. DATAINH or DATAINL).
The   operation   then   proceeds   for   some   number   of   cycles
programmed  in  the  SHIFT_COUNT3:0  field  of  the  LFSRCFG1
register. Completion of the operation is indicated when the DONE
bit in the LFSRCFG1 register is set. (Alternatively, software can
wait an appropriate number of cycles before reading the result.) An autoloading option is available for each LFSR unit to load the
DATAIN register automatically when the SxRBUF register of the
corresponding  SERDES  unit  is  loaded.  LFSR0  and  LFSR2  are
paired  with  SERDES1,  and  LFSR1  and  LFSR3  are  paired  with
SERDES2. Three  registers  in  data  memory  are  used  to  access  the  LFSR
register banks:       Table 4-13  LFSR Registers in Data Memory
Address Name Description 0x23 LFSRH High data byte 0x27 LFSRL Low data byte 0x2B LFSRA Address register