IP2022 User’s Manual—Peripherals www.ubicom.com 307 register allow selecting up to four terms of the register for feedback
into the input (D0), polynomial operation                                                                                                                  control
(POLY_XOR_EN),   and   output   (DOUT)   bit   streams.   A   fifth
multiplexer is only used for generating the output bit stream. The  polynomial  and  residue  registers  are  mapped  as  five  8-bit
registers. The mapping of the residue register is controlled by the
ML_OUT bit of the LFSRCFG3 register, as shown in Figure 4-16. Figure 4-16  Mapping of the Residue Register Input data is shifted out of the 16-bit DATAIN register, which can
be programmed to provide the data LSB-first or MSB-first. Output
data is shifted LSB-first into the 16-bit DATAOUT register. A 32-bit RESCMP register (not shown) can be used to compare
the result in the residue register against an expected value. When
ML_OUT is set, residue register bits 0:31 are compared against
RESCMP bits 0:31. When ML_OUT is clear, residue register bits
39:8 are compared to RESCMP bits 0:31, respectively. If there are
bits   in   the   residue   register   which   do   not   participate   in   the
programmed LFSR operation, be sure that the corresponding bits 515-083.eps RES4 7 0 RES3 7 0 RES2 7 0 RES1 7 0 RES0 7 0 0 Residue Register (ML_OUT = 0) 39 39 Residue Register (ML_OUT = 1) 0