System Architecture—IP2022 User’s Manual 16 www.ubicom.com The hardware peripherals included on-chip are: • 52 I/O port pins • Watchdog Timer • 2 Real-time 8-bit timers • 2 Multifunction 16-bit timers with compare and capture regis-
ters • 2 Serializer/Deserializer (SERDES) channels • 10-bit, 8-channel A/D converter • Analog comparator • Parallel slave peripheral interface There is a single interrupt vector which can be reprogrammed by
software. On-chip peripherals and up to 8 external inputs can raise
interrupts. There are five sources of reset: • RST external reset input • Power-On Reset (POR) logic • Brown-Out Reset (BOR) logic (detects low DVdd condition) • Watchdog Timer • Reset from SPI port programming interface The reset vector is fixed at word address 0xFFF0. An on-chip PLL clock multiplier enables high-speed operation (up
to 100 MHz) from a slow-speed external clock input, crystal, or
ceramic resonator. A CPU clock-throttling mechanism allows fine
control  over  power  consumption  in  modes  that  do  not  require
maximum speed, such as waiting for an interrupt.