Peripherals—IP2022 User’s Manual 298 www.ubicom.com 4.7.3 Using the A/D Converter The following sequence is recommended: 1. Set the ADCTMR register to the correct value for the system
clock speed. 2. Load the ADCCFG register to specify the channel and set
the ADCGO bit. Setting the ADCGO bit enables and resets
the ADC timer. 3. After a period of time (12 timer overflows = 20.8 µs) the con-
version  will complete,  the  ADCGO  bit  will  be  cleared, and
the ADC timer will be disabled. 4. A  timer-based  interrupt  service  routine  can  detect  or  as-
sume the ADCGO bit has been cleared and read the ADC
value. 5. Another load to the ADCCFG register can then be used to
start another conversion. 4.7.4 ADCTMR Register The ADCTMR register is used to specify the number of system
clock  cycles  required  for  a  delay  of  1736  ns,  which  is  used  to
provide the 576 kHz (48 kHz × 12) clock period reference clock for
the A/D converter. At a system clock frequency of 100 MHz, the timer register should
be set to 174 (100 MHz/0.576 MHz). The minimum value that may
be  loaded  into  the  ADCTMR  register  is  2,  so  the  system  clock
must be at least 24 times the ADC sampling frequency for the ADC
to function.