2.0 IP2022 User’s Manual 15 System Architecture The IP2022 CPU executes from a 32K × 16 flash program memory
and an 8K × 16 RAM program memory. The maximum execution
rate is 30 MIPS from flash and 100 MIPS from RAM. Speed-critical
routines  can  be  copied  from  the  flash  memory  to  the  RAM  for
faster execution. The CPU operates on 8-bit data in 128 special-
purpose registers, 128 global registers, and 3840 bytes of data
memory.  The  special-purpose  registers  hold  control  and  status
bits   used   for   CPU   control   and   for   interface   with   hardware
peripherals (timers, I/O ports, A/D converter, etc.). Although   the   philosophy   followed   in   the   design   of   Ubicom
products emphasizes the use of fast RISC CPUs with predictable
execution times to emulate peripheral devices in software (called
ipModule™ software), there are a few hardware peripherals which
are difficult to emulate in software alone (e.g. an A/D converter) or
consume   an   excessive   number   of   instruction   cycles   when
operating  at  high  speed  (e.g.  data  serialization/deserialization).
The  design  of  the  IP2022  incorporates  only  those  hardware
peripherals which can greatly accelerate or extend the reach of
the ipModule™ concept.