Peripherals—IP2022 User’s Manual 270 www.ubicom.com the polarity inversion logic (which can be turned on or off under
software  control)  is  compared  to  the  synchronization  pattern.
Once a match is found, an internal counter is set to zero and data
is  shifted  into  a  shift  register.  The  synchronization  matching
operation  is  then  disabled  until  an  EOP  condition  is  detected,
because    the    synchronization    pattern    potentially    could    be
embedded in the data stream as valid data. The clock/data separation circuit performs Manchester decoding
and NRZI decoding. In addition, bit unstuffing is performed after
the NRZI decoding for the USB bus. This means every bit after a
series of six consecutive ones is dropped. For 10Base-T Ethernet operation, each SERDES is equipped with
a squelch circuit for discriminating between noise, link pulses, and
data. Link pulses are sent periodically to keep the channel open
when no data is being transmitted. The squelch circuit handles link
pulse detection, link pulse polarity detection, carrier sense, and
EOP detection. For UART operation, two internal divide-by-16 circuits are used.
Based on the clock source (either internal or external), the receive
section and the transmit section use two divided-by-16 clocks that
potentially can be out of phase. This is due to the nature of the
UART bus transfers. The receive logic, based on the 16x bit clock
(the clock source chosen by user), will sample the incoming data
for an falling edge. Once the edge is detected, the receive logic
counts 8 clock cycles and samples the number of bits specified in
the  SxRCNT  register  using  the  bit  clock  (which  is  obtained  by
dividing the clock source by 16).