Peripherals—IP2022 User’s Manual 266 www.ubicom.com timer and timer overflow is controlled by the WDPS2:0 bits in the
FUSE1 register, as shown in Table 4-3. The Watchdog Timer register is not visible to software. The only
feature of the Watchdog Timer visible to software is the WD bit in
the STATUS register. 4.6 Serializer/Deserializer (SERDES) There  are  two  SERDES  units  in  the  IP2022,  which  support  a
variety  of  serial  communication  protocols,  including  GPSI,  SPI,
UART,   USB,   and   10Base-T   Ethernet.   By   performing   data
serialization/deserialization   in   hardware,   the   CPU   bandwidth
needed   to   support   serial   communication   is   greatly   reduced,
especially  at  high  baud  rates.  Providing  two  units  allows  easy                        Table 4-3  Watchdog Timer Period
WDPS2:0 (FUSE1 register) Period (ms)* 000 20 001 40 010 80 011 160 100 320 101 640 110 1280 111 2560 * Time periods are approximate