IP2022 User’s Manual—Peripherals www.ubicom.com 255 4.4.2 T1 and T2 Timer Pin Assignments The following table lists the I/O port pins associated with the Timer
T1 and Timer T2 I/O functions. 4.4.3 TxCNTH/TxCNTL Register The    TxCNTH/TxCNTL   register   indicates   the    value   of   the
counter/timer and increments synchronously with the rising edge
of the system clock. This register is read-only. The timer counter
may be cleared by writing to the TxRST bit in the TCTRL register. Reading the TxCNTL register returns the least-significant 8 bits of
the internal TxCNT counter and causes the most-significant 8 bits
of the counter to be latched into the TxCNTH register. This allows
software to read the TxCNTH register later and still be assured of
atomicity. Table 4-2  Timer T1/T2 Pin Assignments I/O Pin Timer T1/T2 Function RA0 Timer T1 Capture 1 Input RA1 Timer T1 Capture 2 Input RA2 Timer T1 External Event Clock Source RA3 Timer T1 Output RB0 Timer T2 Capture 1 Input RB1 Timer T2 Capture 2 Input RB2 Timer T2 External Event Clock Source RB3 Timer T2 Output