Peripherals—IP2022 User’s Manual 252 www.ubicom.com counter is cleared, the TxOUT output is driven high,  unless the
TxCMP1H/TxCMP1L register is clear, in which case the TxOUT
pin is driven low. There  are  two  special  cases.  When  the  TxCMP1H/TxCMP1L
register is clear, the TxOUT pin is driven with a continuous low,
corresponding  to  a  duty-cycle  of  0%.  When  the  value  in  the
TxCMP1H/TxCMP1L   register   is   equal   to   the   value   in   the
TxCAP2H/TxCAP2L register, the TxOUT output is driven with a
continuous high, corresponding to a duty-cycle of 100%. The     behavior     of     the     timers     when     the     value     in     the
TxCMP1H/TxCMP1L  register  are  greater  than  the  value  in  the
TxCAP2H/TxCAP2L register is undefined. The timer is glitch-free no matter when the TxCMP1H/TxCMP1L
register or the TxCMP2H/TxCMP2L register are changed relative
to the value of the internal counter/timer. The new duty cycle or
period  values do not take effect until the  current PWM cycle  is
completed (the counter/timer is reset). Interrupts,   if   enabled   through   the   TxCFG1   register,   can   be
generated  whenever  the  timer  output  is  set  or  cleared.  If  the
TxCMP1H/TxCMP1L   register   is   clear,   or   if   the   value   in   the
TxCMP1H/TxCMP1L   register   is   equal   to   the   value   in   the
TxCAP2H/TxCAP2L register, an interrupt is generated each time
the counter/timer is reset to zero. In PWM mode, the Capture 1 input remains active (if enabled by
the  CPI1EN  bit  in  the  TxCFG1  register)  and,  when  triggered,
captures the current counter/timer value into the TxCAP1 register.