IP2022 User’s Manual—Peripherals www.ubicom.com 251 4.4.1 Timers T1, T2 Operating Modes Each timer can be configured to operate in one of the following
modes: • Pulse-Width Modulation (PWM) • Timer • Capture/Compare PWM Mode In PWM Mode, the timer can generate a pulse-width modulated
signal on its output pin, TxOUT. The period of the PWM cycle (high
+ low) is specified by the value in the TxCAP2H/TxCAP2L register.
The  high  time  of  the  pulse  is  specified  by  the  value  in  the
TxCMP1H/TxCMP1L register. PWM mode can be used to generate an external clock signal that
is  synchronous  to  the  IP2022  system  clock.  For  example,  by
loading TxCMP1H/TxCMP1L with 1 and TxCAP2H/TxCAP2L with
2, a symmetric 50-MHz external clock can be generated from a
100 MHz system clock. In some applications, this can eliminate
crystals or oscillators required to produce clock signals for other
components in the system. The 16-bit counter/timer counts upward. After reaching the value
stored in the TxCMP1H/TxCMP1L register minus one, at the next
clock  edge  the  TxOUT  pin  is  driven  low.  The  counter/timer  is
unaffected   by   this   event   and   continues   to   increment.   After
reaching  the  value  stored  in  the  TxCAP2H/TxCAP2L  register
minus one, at the next clock edge the timer is cleared. When the