Peripherals—IP2022 User’s Manual 242 www.ubicom.com the corresponding bit in the INTF register is set. The bit is set even
if the port pin is not enabled as a source of interrupts. The  interrupt  service  routine  (ISR)  can  check  this  register  to
determine  the  source  of  an  external  interrupt.  If  a  Port  B  pin
enabled for generating interrupts has a set bit in the INTF register,
software must clear the bit prior to exiting to prevent repeated calls
to the ISR. The Port B interrupt logic is asynchronous (e.g. functions without
a clock in clock-stop mode). A side effect is that there is a 2-cycle
delay between the instruction that clears a INTF bit and the bit
being cleared. This means that software must clear the bit at least
2   cycles   before   executing   a   return   from   interrupt   (reti)
instruction. 4.1.8 INTE Register The   INTE   register   consists   of   8   interrupt   enable   bits   that
correspond to the 8 pins of Port B. A Port B pin is enabled as a
source of interrupts by setting the corresponding bit in the INTE
register. The pin is disabled as an interrupt source by clearing the
corresponding INTE bit. 4.1.9 Port Configuration Upon Power-Up On power-up, all the port control registers (RxDIR) are initialized
to   0xFF.   Therefore,   each   port   pin   is   configured   as   a   high-
impedance  input.  This  prevents  any  false  signalling  to  external