Overview—IP2022 User’s Manual 8 www.ubicom.com • Connectivity kits for Internet and communication-intensive ap-
plications 1.2 Architecture 1.2.1 CPU The  IP2022  implements an enhanced Harvard architecture (i.e.
separate   instruction   and   data   memories)   with   independent
address and data buses. The 16-bit program memory and 8-bit
dual-port data memory allow instruction fetch and data operations
to  occur  in  parallel.  The  advantage  of  this  architecture  is  that
instruction fetch and memory transfers can be overlapped by a
multistage  pipeline,  so  that  the  next  instruction  can  be  fetched
from  program  memory  while  the  current  instruction  is  executed
with data from the data memory. Ubicom has developed a revolutionary RISC-based architecture
that is deterministic, jitter free, and completely reprogrammable. The  IP2022  implements  a  four-stage  pipeline  (fetch,  decode,
execute, and write back). At the maximum operating frequency of
100 MHz, instructions are executed at the rate of one per 10 ns
clock cycle. 1.2.2 Serializer/Deserializer Units (SERDES) One of the key elements in optimizing the IP2022 for device-to-
device and device-to-human communication is the inclusion of two