Instruction Set Architecture—IP2022 User’s Manual 212 www.ubicom.com Example: nop    ;assume divisor is 4, so              ;instruction takes 4 cycles
speed div8  ;change divisor to 8,              ;instruction takes 4 cycles
nop    ;instruction takes 8 cycles
speed div1  ;change divisor to 1,              ;instruction takes 8 cycles
nop    ;instruction takes 1 cycle In this example, div1 and div8 are assumed to
be constants defined with appropriate bit settings
for the SPDREG register encoding. If   the   clock   divisor   prior   to   the   first   speed
instruction   is   4,   the   first   nop   and   speed
instructions each take 4 clock cycles. The  first  speed  instruction  changes  the  clock
divisor  to  8,  so  the  second  nop  and  speed
instructions each take 8 clock cycles. The second speed instruction changes the clock
divisor to 1, so the third nop instruction takes 1
clock cycle.