IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 211 SPEED #lit8 Change CPU Speed Operation: SPDREG = lit8 Bits affected: None Opcode: 0000 0001 nnnn nnnn Description: This  instruction  writes  an  8-bit  value  into  the
SPDREG   register.   This   register   controls   the
power-down  options,  system  clock  source,  and
clock divisor used to generate the CPU core clock
from   the   system   clock.   The   format   of   the
SPDREG register is shown below. PWRD1:0—controls    whether    the    PLL    clock
multiplier and OSC oscillator are running.
CLK1:0—selects the system clock source.
CDIV3:0—selects   the   clock   divisor   used   to
generate the system clock. For  a  more  detailed  description  of  these  fields,
see Section 2.1.1. Cycles: 1 instruction cycle (as opposed to clock cycles) 7 6 5 4 3 0 PWRD1:0 CLK1:0 CDIV3:0