Instruction Set Architecture—IP2022 User’s Manual 144 www.ubicom.com Cycles: 1 Example: mov    w,#0x01;load W with 0x01
mov    addrx,w;copy W to ADDRX
mov    w,#0x83;load W with 0x83
mov    addrh,w;copy W to ADDRH
ferase ;erase block This  example  erases  the  512-byte  (256-word)
block from byte address 0x18300 to 0x183FF. The erase operation does not complete and the
flash memory is not accessible until the FBUSY
bit  goes  clear  after  the  ferase  instruction  is
executed. Therefore, any subsequent code that
uses  the  flash  memory  must  either  check  the
state of the FBUSY bit or wait a sufficient number
of delay cycles before proceeding.