IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 143 FERASE Erase Flash Block Operation: See text below Bits affected: FBUSY bit in the XCFG register Opcode: 0000 0000 0000 0011 Description: This  instruction  erases  a  512-byte  (256-word)
block  of  program  flash  memory.  The  ADDRH
register specifies bits 15:8 of the byte address of
the  block.  If  the  block  is  not  in  program  flash
memory,     no     operation     is     performed.     The
instruction is non-blocking (i.e. other instructions
may   execute   before   the   erase   operation   is
complete). After executing this instruction, the FBUSY bit in
the   XCFG   register   is   set.   When   the   erase
operation is complete, the FBUSY bit goes clear.
This   instruction   must   not   be   executed   if   the
FBUSY bit is already set from a previous iread, fwrite,    or   ferase   instruction.    Program execution  out  of  flash  memory  is  not  possible
while   the   FBUSY   bit   is   set,    therefore   this
instruction  can  only  be  executed  from  program
RAM. For more information, see Section 3.7.