www.ubicom.com xiii Table 2-1 Branch Timing .................................................................. 34 Table 2-2 GIE Bit Handling .............................................................. 41 Table 2-3 reti Instruction Options................................................. 44 Table 2-4 Brown-Out Voltage Levels ............................................. 52 Table 2-5 Register States Following Reset................................... 54 Table 3-1 Addressing Mode Summary........................................... 63 Table 3-2 Pipeline Execution........................................................... 80 Table 3-3 Logical Instructions.......................................................... 86 Table 3-4 Arithmetic and Shift Instructions.................................... 87 Table 3-5 Bit Operation Instructions............................................... 93 Table 3-6 Data Movement Instructions .......................................... 93 Table 3-7 Program Control Instructions ......................................... 94 Table 3-8 System Control Instructions ........................................... 95 Table 3-9 Instructions Used for Self-Programming...................... 98 Table 4-1 I/O Port Pin Alternate Functions.................................. 233 Table 4-2 Timer T1/T2 Pin Assignments ..................................... 255 Table 4-3 Watchdog Timer Period................................................ 266 Table 4-4 SERDES Digital Port Pin Usage ................................. 267 Table 4-5 SERDES Analog Port Pin Usage................................ 268 Table 4-6 Protocol Features .......................................................... 274 Table 4-7 Signal Usage .................................................................. 275 Table 4-8 Required Clock Frequencies From PLL..................... 275 Table 4-9 GPSI Interface Signal Usage....................................... 293 Table 4-10 ADC Values .................................................................... 296 Table 4-11 Justification of the ADC Value ..................................... 297 Table 4-12 LFSR Configurations for Various Protocols .............. 303 Table 4-13 LFSR Registers in Data Memory ................................ 308 Table 4-14 LFSRA Register INDEX Encoding.............................. 309 Table 4-15 External Latch Timing Specifications ......................... 323 Table 4-16 SRAM Access Time Specification............................... 324 Table 5-1 ISD/ISP Command Set ................................................. 337 Tables