IP2022 User’s Manual—Instruction Set Architecture
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103
FWRT3:0
The flash memory erase and write timing is derived from the
CPU core clock through a programmable divider. The
FWRT3:0 bits specify the divisor. The time base must be 1 to 2
microseconds. Below 1 microsecond, the flash memory will be
underprogrammed, and data retention is not guaranteed.
Above 2 microseconds, the flash memory will be overpro-
grammed, and reliability is not guaranteed. Because the mini-
mum flash write clock divisor is 2, the minimum clock
frequency for self-programming is 1 MHz.
0000 = 2
1–2 MHz CPU core clock frequency
0001 = 3
2–3 MHz
0010 = 4
3–4 MHz
0011 = 6
4–6 MHz
0100 = 8
6–8 MHz
0101 = 12
8–12 MHz
0110 = 16
12–16 MHz
0111 = 24
16–24 MHz
1000 = 32
24–32 MHz
1001 = 48
32–48 MHz
1010 = 64
48–64 MHz
1011 = 96
64–96 MHz
1100 = 128
96–100 MHz
1101 = 192
Reserved
1110 = 256
Reserved
1111 = 384
Reserved
Name
Description
