Instruction Set Architecture—IP2022 User’s Manual 102 www.ubicom.com FRDTC1:0 The number of system clock cycles for reading the flash mem-
ory using an iread instruction must be specified to prevent
the flash memory access time from being exceeded. Because
the CPU core is subject to changes in speed, the value pro-
grammed in these bits should be appropriate for the fastest
speed that might be used (typically, the faster of the main line
code and the interrupt service routine). The FRDTC1:0 bits
specify the number of CPU core clock cycles required for read
access. 00 =   1 cycle 0–30 MHz system clock frequency 01 =   2 cycles 30–60 MHz 10 =   3 cycles 60–90 MHz 11 =    4 cycles 90–1200 MHz Name Description