IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 101 3.7.2 FCFG Register 7 6 5 4 3 2 1 0 FRDTS1:0 FRDTC1:0 FWRT3:0 Name Description FRDTS1:0 The CPU core clock while executing from flash program mem-
ory must not exceed 30 MHz, otherwise unreliable operation
may result. The IP2022 automatically increases the number of
system clock cycles for each CPU core clock cycle when exe-
cuting from flash, but it is the responsibility of software to load
the FRDTS1:0 bits appropriately for the operating frequency,
as shown below. The actual speed will be the slower of the
speed indicated in the SPDREG register and the speed speci-
fied by the FRDTS1:0 bits. The previous CPU core clock divi-
sor is reinstated when jumping back to program RAM from
program flash memory. 00 =   1 cycle 0–30 MHz system clock frequency 01 =   2 cycles 30–60 MHz 10 =   3 cycles 60–90 MHz 11 =    4 cycles 90–1200 MHz