Instruction Set Architecture—IP2022 User’s Manual 100 www.ubicom.com have no access to the flash memory bits used to implement the
configuration block. 3.7.1 Interrupts During Flash Operations Before  starting  a  flash  write  or  erase  operation,  the  flash  write
timing  compensation  must  be  set  up  properly  for  the  current
speed. The CPU core clock is the time base for the flash write
timing compensation, so it is critical that the CPU core clock speed
is not changed during a flash write or erase operation. Interrupts
may  be  taken  during  a  flash  write  or  erase  operation,  if  the
INTSPD register is set up so the speed does not change when an
interrupt occurs. If the flash read timing compensation is set up for a clock divisor
of   1   (i.e.   fastest   speed),   interrupts   will   not   cause   iread
instructions to fail, so no special precautions need to be taken to
avoid violating the flash read access time.