IP2022 User’s Manual—Instruction Set Architecture www.ubicom.com 99 ADDRX/ADDRH/ADDRL register holds a 24-bit address used to
specify  a  location  in  program  memory.  Like  the  other  pointer
registers (IPH/IPL, DPH/DPL, and SPH/SPL), addition to the low
byte of the register that results in carry will cause the high part of
the  register  (ADDRX/ADDRH)  to  be  incremented.  Subtraction
from the low byte of the register that results in borrow will cause
the high part of the register to be decremented. Software can use the FBUSY bit to check that a previous flash
memory   operation   has   completed   before   executing   another
instruction that accesses flash memory, before jumping or calling
program code in flash memory, and before changing the CPU core
speed. Software must not attempt to execute out of flash memory
while   the   FBUSY   bit   is   set,   because   the   flash   memory   is
unreadable during that time. Code which reads, writes, or erases
flash memory must execute from program RAM, not flash memory.
The CPU core speed must not change while a flash memory read,
write, or erase operation is in progress. Software must wait at least
three cycles before checking the FBUSY bit for completion of the
flash  operation.  It  is  not  necessary  to  check  the  FBUSY  bit  if
enough cycles are allowed for the flash operation to complete. Unlike  RAM,  flash  memory  requires  an  explicit  erase  operation
before being written. The ferase instruction is used to erase a
512-byte (256-word) block of flash memory. After the block has
been erased, individual words can be written with the  fwrite
instruction. For example, an ferase instruction executed on any
address   from   0x10000   to   0x100FE   erases   the   whole   block
spanning  those  addresses.  The  self-programming  instructions