Instruction Set Architecture—IP2022 User’s Manual 98 www.ubicom.com Blocking instructions take 4 cycles to complete, and prevent other
instructions from executing. Non-blocking instructions occupy the
CPU  pipeline  for  only  one  cycle,  but  they  launch  a  multi-cycle
operation which is not complete until indicated by the FBUSY bit
in the XCFG register becoming clear. Read and write operations that involve program memory use two
registers. The DATAH/DATAL register is a 16-bit data buffer used
for    loading    or    unloading    data    in    program    memory.    The Table 3-9  Instructions Used for Self-Programming iread
ireadi Blocking     Non-
Blocking Blocking Blocking N/A iwrite
iwritei Blocking nop Blocking nop N/A fwrite nop     Non-
Blocking nop nop nop ferase nop     Non-
Blocking nop nop nop