Instruction Set Architecture—IP2022 User’s Manual 86 www.ubicom.com description of what the instruction does, the number of instruction
cycles required for execution, the binary opcode, and the flags in
the STATUS register affected by the instruction. Although the number of clock cycles for execution is typically 1, for
the skip instructions the exact number of cycles depends whether
the skip is taken or not taken. Taking the skip adds 1 cycle. The
effect  of  extended  skip  instructions  (i.e.  a  skip  followed  by  a loadh, loadl, or page instruction) is not shown. Table 3-3  Logical Instructions Assembler Syntax Description Opcode and fr,w AND fr,W into fr 1 0001 011f ffff ffff Z and w,fr AND W,fr into W 1 0001 010f ffff ffff Z and w,#lit8 AND W,literal
into W 1 0111 1110 kkkk kkkk Z not fr Complement fr
into fr 1 0010 011f ffff ffff Z not w,fr Complement fr
into W 1 0010 010f ffff ffff Z or fr,w OR fr,W into fr 1 0001 001f ffff ffff Z or w,fr OR W,fr into W 1 0001 000f ffff ffff Z or w,#lit8 OR W,literal into W 1 0111 1101 kkkk kkkk Z