© 2000 Ubicom, Inc. All rights reserved. - 3 - www.ubicom.com Pre-Built Software Modules
•    Selection of physical interfaces –   10Base-T Ethernet
–   USB
–   UART       –   I²C
      –   SPI
      –   Parallel slave
•    Complete TCP/IP stack Software Support
•    Red Hat GNUPro tools –   GCC ANSI C compiler and assembler, linker, utili-            ties, GNU debugger, and IDE
•    Nohau in-circuit debugger       –   Seehau Interface
      –   USB-based debug hardware
      –   Assembler
•    Library of  off-the-shelf  ipModules (Ethernet,  serial  in-       terfaces, USB interface, etc.)
•    Evaluation  kits  for  Internet  and  communication-inten- sive applications 1.3    Architecture 1.3.1  CPU
The IP2022 implements an enhanced Harvard architec-
ture with two separate memories that have independent
address and data buses, a 16-bit program memory, and
an  8-bit  dual-port  data  memory.  This  allows  instruction
fetch and data operations to occur in parallel. The advan-
tage of this architecture is that instruction fetch and mem-
ory transfers can be overlapped by a multistage pipeline,
so that the next instruction can be fetched from program
memory  while  the  current  instruction  is  executed  with
data from the data memory.
Ubicom   has   developed   a   revolutionary   RISC-based
architecture  that  is  deterministic,  jitter  free,  and  com-
pletely reprogrammable.
The   IP2022   implements   a   four-stage   pipeline   (fetch,
decode, execute, and write back). At the maximum oper-
ating frequency of 100 MHz, instructions are executed at
the rate of one per 10 ns clock cycle. 1.3.2  Serializer/Deserializers
One  of  the  key  elements  in  optimizing  the  IP2022  for
device-to-device and device-to-human communication is
the   inclusion   of   on-chip   serializer/deserializers.   This
hardware decodes data and lets it be translated from one
format  to  another,  allowing  the  IP2022  to  be used as  a
protocol converter in bridge and gateway applications.
There  are two serializer/deserializer  units in the IP2022
that  support  a  variety  of  protocols,  including  SPI,  I²C,
UART, USB, and 10Base-T Ethernet. By performing data
serialization  and  deserialization  in  hardware,  the  CPU
bandwidth  needed  to  support  serial  communications  is
greatly reduced, especially at high baud rates. Providing
two units allows easy implementation of protocol conver-
sion or bridging functions, such as a USB-to-I²C bridge.
1.3.3  Low-Power Support
Particular  attention  has  been  paid  to  minimizing  power
consumption. For example, an on-chip PLL allows use of
a lower-frequency external source (e.g., an inexpensive 4
MHz crystal oscillator can be used to produce a 100 MHz
internal operating frequency), which reduces both power
consumption and EMI. In addition, software can change
the  execution  speed  of  the  CPU  to  reduce  power  con-
sumption, and a mechanism is provided for automatically
changing the speed on entry and return from an interrupt
service routine. The SPEED instruction specifies power-
saving modes that include a clock divisor between 1 and
128. This divisor only affects the clock to the CPU core,
not the timers. The SPEED instruction also specifies the
clock   source   (OSC1   clock,   RTCLK   oscillator,   or   PLL
clock multiplier), and whether to disable the OSC1 clock
oscillator  or  the  PLL.  The  SPEED  instruction  executes
using the current clock divisor.
1.3.4  Memory
The  IP2022  CPU  executes  from  a  32K  ×  16  flash  pro-
gram memory and an 8K × 16 RAM program/data mem-
ory. The instruction RAM can alternative be used for data
storage. In addition, the ability to write into the program
flash  memory,  allows  flexible  non-volatile  RAM  imple-
mentation. The maximum execution rate is 40 MIPS from
flash  and  100  MIPS  from  RAM.  Speed-critical  routines
can  be  copied  from  the  flash  memory  to  the  RAM  for
faster  execution.  The  IP2022  has  a  mechanism  for  in-
system programming of its flash and RAM program mem-
ories through a four-wire SPI interface, and software has
the  ability  to  reprogram  the  program  memories  at  run
time.   This   allows   the   functionality   of   a   device   to   be
changed in the field over the Internet.