© 2000 Ubicom, Inc. All rights reserved. - 2 - www.ubicom.com 1.2    Key Features CPU Features
•    RISC engine core with DC to 100 MHz operation
•    10 ns instruction cycle
•    Compact single-word (16-bit) instruction set
•    Single-cycle instruction execution on most instructions
•    1 instruction per clock (3 clocks per branch)
•    16-bit instructions
•    Sixteen-level   hardware   stack   for   high-performance       subroutine linkage
•    8 × 8 signed/unsigned single-cycle multiply
•    Pointers and Stack operation optimized for C compiler On-chip Memory
•    64 Kbyte (32kx16) program flash memory
•    16 Kbyte (8kx16) program/data RAM
•    4 Kbyte Data RAM
•    Self-programming  with  built-in  charge  pump:  instruc- tions to read, write, and erase Fast and Deterministic Program Execution and Inter-
rupt Response
•    Predictable  execution  rate  for  hard  real-time  applica-       tions
•    Fast  and  deterministic  3-cycle  internal  interrupt  re- sponse
–   30 ns internal interrupt response at 100 MHz includ-            ing context save
•    Hardware  save/restore  of   register  context  (PC,  W, STATUS, MULH, SPDREG, IPH, IPL, DPH, DPL, SPH,
SPL, ADDRH, ADDRL, DATAH, DATAL) Multiple  Networking  Protocols  and  Physical  Layer
Support Hardware
•    Two  full-duplex  serializer/deserializer  (SerDes)  chan- nels for 10BaseT (MAC/PHY), USB, and other fast se-
rial protocol support
–   Embedded connectivity nodes
–   Two channels for protocol bridging –   I²C, UART, SPI, Microwire/PLUS General-Purpose Hardware Peripherals
•    Two 16-bit timers with 8-bit prescalers supporting:       –   Timer mode
      –   PWM mode
      –   Capture/Compare mode
•    Slave parallel/host interface, 8/16-bit selectable for use       as a communications co-processor
•    One 8-bit timer with programmable 15-bit prescaler
•    One 8-bit real-time clock/counter with programmable 8-       bit prescaler and 32 KHz crystal input
•    Watchdog timer with postscaler
•    On-chip PLL clock multiplier with pre- and post-divider –   4  MHz  input produces 100 MHz  internal  operating            frequency
•    10-bit, 8-channel ADC with 1/2 LSB accuracy
•    Analog comparator with hysteresis enable/disable
•    Brown-out minimum supply voltage detector
•    External interrupt inputs on 8 pins (Port B) Sophisticated  Power  and  Frequency/Clock  Manage-
ment Support
•    Operating voltage of 2.3V to 2.7V
•    Switching the system clock frequencies between differ-       ent clock sources
•    Changing the core clock using a selectable divider
•    Shutting down the PLL and/or the OSC input
•    Controlling the speed of the Core by SPEED instruction
•    Power-On-Reset (POR) logic Flexible I/O
•    52 I/O Pins
•    3.3V drive, 5V-tolerant inputs
•    Symmetrical output drive
•    Port A pins capable of sourcing/sinking 24 mA
•    Selectable I/O operation synchronous to the CPU core clock Programming and Debugging Support
•    Updatable application program       –   Run-time self programming
•    On-chip in-system programming support with SPI inter-       face
•    On-chip in-system debugging support logic with dedi-       cated SPI interface
      –   Debugging at full IP2022 operating speed
•    Programming at device supply voltage level
•    Real-time emulation, program debugging, and integrat- ed software development environment offered by lead-
ing third-party tool vendors