2
FUSEX Word
Register
Bits 8, 9, and 11 are used for internal
RC oscillator trimming.
Bit 10 is used for package selection.
Bit 7 is used to enable 8-bit OPTION
register and 8-level Stack.
Bit 6 used for ADD/SUB with C
enable.
Bits 4 and 5 are used for Brown-Out-
Reset.
Bits 2 and 3 used for Brown-Out Reset
Trimming.
Bits 0 and 1 used for Program and Data
Memory Size selection
All bits the same with the exception of:
Bit 10 is used for Sleep Clock Disable.
Bit 7 is unused.
Bits 0 and 1 used for Delay Reset
Timer period selection.
Delay Reset Timer
(DRT) Timeout
Period
Fixed delay for automatic wake-up
from the power down mode.
A 2-bit field (DRT1: DRT0, bits 0 and
1) ) at the FUSEX Word register can be
used to specify the DRT timeout period
that results in an automatic wake-up
from the power down mode.
Sleep Clock Disable
Not available.
Bit 11 (SLEEPCLK) of the FUSEX
word register is used to enable
operation of the clock during the power
down mode.
Program Memory
Organized as 2k, 12-bit wide words.
Organized as 4K, 12-bit wide words.
Program Counter
Upon reset, the program counter is
initialized to 07FFh.
Upon reset, the program counter
initialized to 0FFFh.
Data Memory
Consists of 136 bytes of RAM,
organized as eight banks of 16
registers, plus an additional bank of 16
global registers, 8 of which are
general-purpose RAM locations.
Consists of 262 bytes of RAM
organized into 16 banks (banks 0 to F),
each containing 16 registers, plus an
additional bank of 16 "global"
registers, 6 of which are general-
purpose RAM locations.