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SX IrDA Virtual Peripheral Implementation
AN16
3.0
IrDA Layer Descriptions
The following sections describe each of the layers in the
IrDA stack in more detail.
3.
1
PHYSICAL LAYER
The physical layer consists of an IrDA UART to convert
octets of data to an IR pulse stream and to process the
received pulse stream into octets of data.
IR communication is inherently half-duplex in nature as
the IR emitter used for transmission is physically close to
the IR detector used for reception thus the detector will
always detect what is being transmitted. Furthermore a
minimum turnaround time must be respected to allow the
daylight correction on the detector to recover from the
transmission.
The octet encoding is dependant on the class of the
speed, and for “ASYNC” speeds (9600-115200bps) the
bit timing is the same as a conventual UART but based
on pulses. A ‘0’ is encoded as a pulse and a ‘1’ is
encoded as no pulse. The bit format is 1 start bit, 8 data
bits, and 1 stop bit (no parity). The octet will start with a
pulse for the start bit (start bit = ‘0’), followed by 8 data
pulses/no-pulses, followed by a no-pulse for the stop bit
(stop bit = ‘1’ - return to idle). The pulse can be of any
width between 1.6us (3/16ths of the bit time at
115200bps) and 3/16ths of the total bit time for the UART
speed.
3.1.1 SX Timing
The IrDA Virtual Peripheral implementation uses a con-
stant pulse time of 2.16us (within the IrDA specifications)
regardless of the speed. This time is 4/16ths of the bit
time at 115200 allowing the use of a divide by 4 rather
than a divide by 16 counter and reducing the counter res-
olution to 8-bit. The timer ISR routine will be executed
every 2.16us (108 clock cycles @ 50MHz) thus 4 inter-
rupts will be received per bit at the highest speed of
115200bps.
The HP HDSL1001 IrDA transceiver (which is described
in the hardware section) has the following signal proper-
ties:
• RxIdle High
• TxIdle Low
It
should
also
be
noted
that
the
IR
transceiver
LED
timing
is
completely
software
controlled.
If
the
SX
device
leaves
the
LED
on
continually
then
the
IR
transceiver
may
be
permanently
damaged
as
it
will
be operating at 4.5 times its absolute maximum aver-
age current rating.
For reception the pulse will generate an interrupt flag
(falling edge) but will not generate an interrupt. If an inter-
rupt occurs during the ISR execution the SX will not re-
enter the ISR. By using the interrupt flag (rather than rais-
ing an interrupt) no interrupts are missed, even during
ISR processing. The flag will be detected the next time
the timer interrupts, and will be processed then.
3.1.2 Physical Layer API
When a byte has been received the global IrdaRxAvail
flag will be set and the data will be available from the
IrdaRxData register in the IsrBank.
A byte can be transmitted by first storing it in the
IrdaTxData register in the IsrBank and then by set-
ting the global flag IrdaTxStart. When the byte has
been transmitted the ISR will set the global flag IrdaTx-
Empty.
3.
2
FRAMING LAYER
For transmission the framing layer adds the required
framing information to the payload data. For reception
the framing layer removes the framing information to
recover the payload data. The framing information con-
sists of turn-around delay bytes, beginning and end of
frame bytes, a 16-bit CRC check, and the application of
transparency bytes.
3.2.1 Frame Format
Framing is described in the IrDA IrLAP documentation
(pages 112-118). The format of a frame is shown in Fig-
ure 3-1.
The initial beginning-of-frame bytes (BOFs) take care of
the turnaround delay required for a IR receiver to recover
after transmission. Initial BOFs are send as $FF rather
than the BOF byte $C0 as recommended by the IrLAP
specification.
The frame-check-sequence (FCS) is a 16-bit CCITT CRC
covering all the payload data prior to the application of
any transparency bytes required. The traditional look-up
table approach requires a 512 byte look-up table thus is
unrealistic to implement on a small communications con-
troller. The FCS is instead calculated on a byte-by-byte
basis as they are transmitted/received using just 21
words of sequentially executed code. The derivation of
the FCS calculation can be found in Appendix A.
For reception all bytes received after the BOF (and after
transparency recovery) are included in the FCS calcula-
tion until the end-of-frame (EOF) byte is received (i.e.
including the FCS bytes). When the EOF is received the
calculated FCS in memory is compared to the constant
$F0B8 to determine the validity of the frame. It should be
noted that the FCS is defined as the last two bytes prior
to the EOF byte thus to remove the FCS all payload data
passes through a 2-byte FIFO buffer before being
passed as payload data to the higher layer.
Initial BOFs
BOF
($C0)
Payload Data
FCS
(2 bytes)
EOF
($C1)
Figure
3-1. Frame Format
