ON 20091208@9:51:35 AM at page:
On a web page you were interested in at:
http://techref.massmind.org/microchip/math/radix/ah2b-1d4b.htm#40154.9770486111
James Newton[JMN-EFP-786] published post 40154.9770486111

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I read this last suggestion to use this instruction and ended up spending a few days trying to figure out why it is unpredictable.  This does not work (at least not on a 12F629 *and* the assembler does not even generate a warning):<BR>
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btfsc	WREG,6  ; not all pics can do this...<BR>
<BR>
That assembles to 1A00 == &quot;btfsc 0, 6&quot; and since W is a SFR (special function register 0) and NOT a File Register which btfsc operates on, it tests the correct bit in the wrong register.  &quot;btfsc 0,6&quot; references INDF (File Register 0, the register pointed at by FSR), not W.<BR>
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There is no place in the instruction encoding for this bit test instruction to specify the difference between WREG at 0 and INDF at 0.  so that code &quot;btfsc WREG, 6&quot; really executes as &quot;btfsc INDF, 6&quot;.  Compact, but broken.<BR>
<BR>
best regard from Barry L. Kramer in Mohnton PA<BR>

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ON 20091224@11:43:50 AM at page:
On a web page you were interested in at:
http://techref.massmind.org/microchip/math/radix/b2bu-16b5d.htm#40171.4136458333
James Newton[JMN-EFP-786] published post 40171.4136458333

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Perfect, thank you all!<BR>

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