;----------------------------------------------------------------------------- ; Input: ; a1:a0 - 14 bit dividend (a0 - lower byte) ; b1:b0 - 15 bit divisor in 7Q8 format (b1 is integer, b0 is ; fractional) ; Output: ; c1:c0 - 15 bit quotient in 7Q8 format ; ; Size: 27 words ; Time: 2+3+3+15*(2+3+7+5)-1+2=264 instruction cycles ; ; March 13, 2001 by Nikolai Golovchenko ; March 14, 2001 optimized by Scott Dattalo ;----------------------------------------------------------------------------- div_uint14_fxp7q8_fxp7q8 ;left align the dividend ; (shift accumulator left 1 bit to get the first result bit weight ; equal to 128) clrc rlf a0, f rlf a1, f ;carry is cleared here ;initialize registers clrf c0 ;clear result - it will be used clrf c1 ;to shift zeroes to dividend bsf c0, 1 ;15 iterations div_loop rlf a0, f ;and shift out next bit of dividend rlf a1, f ;to remainder movf b0, w ;load w with lower divisor byte skpnc ;if remainder positive - subtract, goto div_add ;if negative - add ;subract subwf a0, f movf b1, w skpc incfsz b1, w subwf a1, f goto div_next div_add ;add addwf a0, f movf b1, w skpnc incfsz b1, w addwf a1, f div_next ;here carry has a new result bit rlf c0, f ;shift in next result bit rlf c1, f skpc goto div_loop return ;-----------------------------------------------------------------------------