Mnemonic,    Operands ADDWF f, d, a BYTE-ORIENTED FILE REGISTER OPERATIONS Add W and f 1,2 C,DC,Z,OV,N 0010 01da ffff ffff 1 Description ADDWFC   f, d, a Add W and Carry bit to f 1,2 C,DC,Z,OV,N 0010 00da ffff ffff 1 Cycles 16-Bit Instruction Status
Affected Notes MSB LSB Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB,1), the value used will be that
value present on the pins themselves.  For example, if the data latch is '1' for a pin configured as input and
is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles.  The
second cycle is executed as a NOP. ANDWF f, d, a AND W with f 1,2 Z,N 0001 01da ffff ffff 1 CLRF f, a Clear f 2 Z 0110 101a ffff ffff 1 COMF f, d, a Complement f 1,2 Z,N 0001 11da ffff ffff 1 CPFSEQ   f, a Compare f with W, skip = 4 0110 001a ffff ffff 1 (2 or 3) CPFSGT   f, a Compare f with W, skip > 4 0110 010a ffff ffff 1 (2 or 3) CPFSLT   f, a Compare f with W, skip < 1,2 0110 000a ffff ffff DECF f, d, a Decrement f 1-4 C,DC,Z,OV,N 0000 01da ffff ffff 1 DECFSZ   f, d, a Decrement f, Skip if 0 1-4 0010 11da ffff ffff DCFSNZ   f, d, a Decrement f, Skip if Not 0 1,2 0100 11da ffff ffff INCF f, d, a Increment f 1-4 C,DC,Z,OV,N 0010 10da ffff ffff 1 INCFSZ   f, d, a Increment f, Skip if 0 4 0011 11da ffff ffff INFSNZ   f, d, a Increment f, Skip if Not 0 1,2 0100 10da ffff ffff IORWF f, d, a Inclusive OR W with f 1,2 Z,N 0001 00da ffff ffff 1 MOVF f, d, a Move f 1 Z,N 0101 00da ffff ffff 1 MOVFF f_s ,f_d 1100 ffff ffff ffff 2 1111 ffff ffff ffff MOVWF f, a Move W to f 0110 111a ffff ffff 1 MULWF f, a Multiply W with f 0000 001a ffff ffff 1 NEGF f, a Negate f 1,2 C,DC,Z,OV,N 0110 110a ffff ffff 1 RLCF f, d, a Rotate Left f through Carry C,Z,N 0011 01da ffff ffff 1 RLNCF f, d, a Rotate Left f (No Carry) 1,2 Z,N 0100 01da ffff ffff 1 RRCF f, d, a Rotate Right f through Carry C,Z,N 0011 00da ffff ffff 1 RRNCF f, d, a Rotate Right f (No Carry) Z,N 0100 00da ffff ffff 1 SETF f, a Set f 0110 100a ffff ffff 1 SUBFWB   f, d, a Subtract f from W w/borrow 1,2 C,DC,Z,OV,N 0101 01da ffff ffff 1 SUBWF f, d, a Subtract W from f C,DC,Z,OV,N 0101 11da ffff ffff 1 SUBWFB   f, d, a Subtract W from f w/borrow 1,2 C,DC,Z,OV,N 0101 10da ffff ffff 1 SWAPF f, d, a Swap nibbles if f 4 0011 10da ffff ffff 1 TSTFSZ   f, a Test f, skip if 0 0110 011a ffff ffff 1 (2 or 3) 1 (2 or 3) 1 (2 or 3)
1 (2 or 3) 1 (2 or 3)
1 (2 or 3) Move f_s (source) 1st word to   f_d (destination) 2nd word 1,2 XORWF f, d, a Exclusive OR W with f Z,N 0001 10da ffff ffff 1 BCF f, b, a BIT-ORIENTED FILE REGISTER OPERATIONS Bit Clear f 1,2 1001 bbba ffff ffff 1 BSF f, b, a Bit Set f 1,2 1000 bbba ffff ffff 1 BTFSC f, b, a Bit Test f, Skip if Clear 3,4 1011 bbba ffff ffff BTFSS f, b, a Bit Test f, Skip if Set 3,4 1010 bbba ffff ffff BTG f, b, a Bit Toggle f 1,2 0111 bbba ffff ffff 1 1 (2 or 3)
1 (2 or 3) 4: Some instructions are 2-word instructions.  The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits
ensures that all program memory locations have a valid instruction. 5:   If the Table Write starts the write cycle to internal memory, the write will continue until   f = 8-bit register file address   d = destination, W (0) or f (1)   a = access bit, (0) access bank       or (1) bank selected by BSR Mnemonic,    Operands BC n CONTROL OPERATIONS Branch if Carry 1110 0011 nnnn nnnn 1 (2) Description BN n Branch if Negative 1110 0110 nnnn nnnn 1 (2) Cycles 16-Bit Instruction Status
Affected Notes MSB LSB BNC n Branch if Not Carry 1110 0011 nnnn nnnn 1 (2) BNN n Branch if Not Negative 1110 0111 nnnn nnnn 1 (2) BNOV n Branch if Not Overflow 1110 0101 nnnn nnnn 1 (2) BNZ n Branch if Not Zero 1110 0001 nnnn nnnn 2 BOV n Branch if Overflow 1110 0100 nnnn nnnn 1 (2) BRA n Branch Unconditionally 1101 0nnn nnnn nnnn BZ n Branch if Zero 1110 0000 nnnn nnnn 1 (2) CALL n,s Call subroutine 1st word 1110 110s kkkk kkkk   2nd word 1111 kkkk kkkk kkkk CLRWDT   -- Clear Watchdog Timer TO,PD 0000 0000 0000 0100 1 DAW -- Decimal Adjust W C 0000 0000 0000 0111 GOTO n Goto address 1st word 1110 1111 kkkk kkkk   2nd word 1111 kkkk kkkk kkkk NOP -- No Operation 0000 0000 0000 0000 1 NOP 1111 xxxx xxxx xxxx 1 POP 0000 0000 0000 0110 1 PUSH -- Push top of return stack 0000 0000 0000 0101 1 RCALL n Relative Call 1101 1nnn nnnn nnnn 2 RESET Software device RESET All 0000 0000 1111 1111 1 RETFIE   s Return from interrupt GIE/GIEH, 0000 0000 0001 000s 2 PEIE/GIEL RETLW k Return with literal in W 0000 1100 kkkk kkkk 2 RETURN   s Return from Subroutine 0000 0000 0001 001s 2 SLEEP -- Go into Standby mode TO,PD 0000 0000 0000 0011 1 1 (2) 2 1
2 -- No Operation (Note 4) -- Pop top of return stack ADDLW k LITERAL OPERATIONS Add literal and W C,DC,Z,OV,N 0000 1111 kkkk kkkk 1 ANDLW k AND literal with W Z,N 0000 1011 kkkk kkkk 1 IORLW k Inclusive OR literal with W Z,N 0000 1001 kkkk kkkk 1 LFSR f,k Move literal (12-bit) 2nd 1110 1110 00ff kkkk 2   word to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 0000 0001 0000 kkkk 1 MOVLW k Move literal to W 0000 1110 kkkk kkkk 1 MULLW k Multiply literal with W 0000 1101 kkkk kkkk RETLW k Return with literal in W 0000 1100 kkkk kkkk 2 SUBLW k Subtract W from literal C,DC,Z,OV,N 0000 1000 kkkk kkkk XORLW k Exclusive OR literal with W Z,N 0000 1010 kkkk kkkk 1 1
1 TBLRD * DATA MEMORY <-> OPERATIONS Table Read 0000 0000 0000 1000 2 TBLRD *+ Table Read post-increment 0000 0000 0000 1001 TBLRD *- Table Read post-decrement 0000 0000 0000 1010 TBLRD +* Table Read pre-increment 0000 0000 0000 1011 TBLWT Table Write 5 0000 0000 0000 1100 2 TBLWT *+ Table Write post-increment 0000 0000 0000 1101 TBLWT *- Table Write post-decrement 0000 0000 0000 1110 TBLWT +* Table Write pre-increment 0000 0000 0000 1111   b = bit address within an 8-bit       file register   W = WREG (accumulator)   k = literal, constant, or label   x = don't care   C = Carry Status bit DC = Digit Carry Status bit   Z = Zero Status bit OV = Overflow Status bit   N = Negative Status bit   s = Fast Call/Return select bit   n = relative address (branch)       or a direct address