;--------------------------------------------------------------------------- ; Fixed point divide routine - From Microchip's application note ;--------------------------------------------------------------------------- ; RCS Header $Id: fxdb.a17 2.2 1996/06/11 21:42:11 F.J.Testa Exp $ ; $Revision: 2.2 $ ; PIC17 FIXED POINT DIVIDE ROUTINES B ; ; Input: fixed point arguments in AARG and BARG ; ; Output: quotient AARG/BARG followed by remainder in REM ; ; All timings are worst case cycle counts ; ; It is useful to note that the additional unsigned routines requiring a non-power of two ; argument can be called in a signed divide application where it is known that the ; respective argument is nonnegative, thereby offering some improvement in ; performance. ; ; Routine Clocks Function ; ; FXD1608U 196 16 bit/08 bit -> 16.08 unsigned fixed point divide ; ;********************************************************************************************** MSB equ 7 LSB equ 0 #define _C ALUSTA,0 #define _Z ALUSTA,2 UDIV1608 macro ; ; restore = 9/15 clks, nonrestore = 8/11 clks ; ; Max Timing: 8*9+1+8*15 = 193 clks max ; ; Min Timing: 8*8+1+8*11 = 153 clks min ; ; PM: 8*9+1+8*15 = 193 DM: 4 ; variable t variable t = 0 while t < 8 RLCF ACCB0,W RLCF REMB0, F MOVFP BARGB0,WREG SUBWF REMB0, F BTFSC _C GOTO UOK68#v(t) ADDWF REMB0, F BCF _C UOK68#v(t) RLCF ACCB0, F variable t=t+1 endw CLRF TEMP, F variable t = 8 while t < D'16' RLCF ACCB1,W RLCF REMB0, F RLCF TEMP, F MOVFP BARGB0,WREG SUBWF REMB0, F CLRF WREG, F SUBWFB TEMP, F BTFSC _C GOTO UOK68#v(t) MOVFP BARGB0,WREG ADDWF REMB0, F CLRF WREG, F ADDWFC TEMP, F BCF _C UOK68#v(t) RLCF ACCB1, F variable t=t+1 endw endm ;********************************************************************************************** ;********************************************************************************************** ; ; 16/8 Bit Unsigned Fixed Point Divide 16/08 -> 16.08 ; ; Input: 16 bit unsigned fixed point dividend in AARGB0, AARGB1 ; 8 bit unsigned fixed point divisor in BARGB0 ; ; Use: CALL FXD1608U ; ; Output: 16 bit unsigned fixed point quotient in AARGB0, AARGB1 ; 8 bit unsigned fixed point remainder in REMB0 ; ; Result: AARG, REM <-- AARG / BARG ; ; Max Timing: 1+193+2 = 196 clks ; ; Min Timing: 1+153+2 = 156 clks ; ; PM: 1+193+1 = 195 DM: 4 ; FXD1608U CLRF REMB0, F UDIV1608 RETLW 0x00