From Regulus Berdin
;********************************************************************** ; Adjustable delay from 11-256 cycles (for 14 bit core) ; W = count, cycle count excludes loading of W ; by Regulus Berdin delay: addlw -(.10+1) ;2+1 remove 1 count more for carry correction addlw -4 ; 1 skpnc ; 1/2 goto $-2 ; 2 sublw 0xFF ; 1 addwf PCL,f ; 2 delay7 nop ; delay adjuster delay6 nop ; delay5 nop ; delay4 return ;2
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