On-Chip Debugger Specification DS51242A-page 8 ã 2001 Microchip Technology Inc. 2.4 Using the On-Chip Debugger Registers There are two registers associated with debugger control: the ICKBUG and
BIGBUG registers (Figure 2.2 and Figure 2.3.) Between these two registers,
there are 3 bits for debugger control and 13 bits for breakpoint address
specification. INBUG - Set/cleared automatically when entering/exiting debug executive. A four (4) instruction cycle delay will prevent the new state of zero from being
recognized by the core to allow a safe debugger exit. When set, interrupts are
disabled (regardless of the state of the GIE bit) and the debugger HALT is
disabled. This prevents reentry into the debugger while communicating with
computer software. FREEZ - When FREEZ is set, TMR0, TMR1 and TMR2 and their prescalers freeze at a break (suspend counting). The SSP, A/D converter and USART
state machines will also suspend upon the assertion of the FREEZ bit. Status
flag bits that are altered by register read operations are unaffected while
FREEZ is asserted. SSTEP - Enables single step operation. After a return to normal operation (INBUG=0), if SSTEP is set, the on-chip logic will allow one user instruction to
execute before the on-chip debugger is reentered. BKAnn - Break address nn. These bits are cleared at POR. No other reset clears the bits, (i.e., a MCLR cannot change the breakpoint address value). Figure 2.2:  ICKBUG Register (Address 18Eh) R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INBUG FREEZ SSTEP BKA12 BKA11 BKA10 BKA09 BKA08 R        = Readable bit
W   = Writable bit
U = Unimplemented bit,             read as ‘0’
- n  = Value at POR reset bit7 bit0 bit 7: INBUG: On-chip debugger activity status 1 = Device is executing on-chip debugger code
0 = Device is executing user code
(This bit is read only; set from on-chip halt or breakpoint occurrence; only clear by RETURN) bit 6: FREEZ: on-chip debugger freeze mode 1 = Peripherals will freeze when INBUG=1
0 = Peripherals will not freeze when INBUG=1 bit 5: SSTEP: Single Step Enable 1 = Program will execute 1 instruction word of user code upon RETURN from debug code
0 = Program will execute multiple instruction words of user code bit 4-0: BKA: Breakpoint Address When writing, represents the requested breakpoint address.
When reading, represents the value of the PC at last breakpoint, halt, or single step operation.