ã 2001 Microchip Technology Inc. DS51242A-page 11 PIC16F87X Debugger Control 2.7.2 Halting Execution by Address Breakpoint For the conditions specified in Section 2.7, another HALT method is by
address breakpoint. The ICKBUG and BIGBUG registers contain a 13-bit value
(BKAnn) that is compared against the current PC value. When the values are
equal, then the circuit will generate a halt signal on that cycle. Power-up initializations the state of the ICKBUG and BIGBUG registers to
0x0000, equal to the reset vector. Disabling the breakpoints is implemented by setting a breakpoint address that
lies in the address space of the on-chip debugger (ex: 0x1F00.) 2.7.3 Halting Execution by Single Stepping For the conditions specified in Section 2.7, another HALT method is by single
step. Upon exit of the debug routine by the return instruction, if the SSTEP
bit is set, the on-chip debugger logic will generate a HALT signal timed to
allow one instruction execution. After this, the device will reenter the on-chip
debugger routine in the same fashion as the external (I/O pin) halt. 2.8 Additional Considerations In addition to the logic required to support the on-chip debugger as described
in the above sections, there are several issues of which to be aware. •  Watchdog Timer will still be functional with no special modes associated with on-chip debugger. •  The reset, POR and BOR logic will still be functional with no special modes associated with the on-chip debugger. Note: A hardware halt after reset will execute location 0x0000 and then
skid  to  0x0001.  Therefore,  a  NOP  is  recommended  at  location
0x0000.