18F452: ADDLW   -3   
30F3013: dc1:     add.b     #-3,W0     ;3-cycle delay loop
18F452: BC   dc1   
30F3013:       bra     C,dc1     
18F452: BTFSS   WREG   1
30F3013:      btss.b     WREG,#1     
18F452: BRA   dc2   
30F3013:       bra     dc2     ;W=0xFD - no extra delay needed
18F452: RRCF   WREG   F
30F3013:      rrc.b     WREG     ;If the LSB is set (W=0xFF) then set C
18F452: BC   dc2   
30F3013:       bra     C,dc2     ;add a cycle delay for W=0xFF but not 0xFE
18F452: RETURN      
30F3013: dc2:     return