;------------------------------------------------------------
; DelayCycles:
;
; Input:   W -- the desired delay
; Output:  Returns after W+7 cycles

DelayCycles:

dc1:        ADDLW        -3        ;3-cycle delay loop
       BC        dc1

 ; W now contains either -3 (0xFD), -2 (0xFE) or -1 (0xFF).
 ; The -2 case needs to be delayed an extra cycle more than
 ; the -3 case, and the -1 case needs yet another cycle of delay.
 ;
 ; Examine the bottom two bits of W to determine the exact delay
 ;

       BTFSS   WREG,1
        BRA        dc2        ;W=0xFD - no extra delay needed
       RRCF        WREG,F  ;If the LSB is set (W=0xFF) then set C
       BC        dc2     ;add a cycle delay for W=0xFF but not 0xFE
dc2:    RETURN