A core-dump implementation for PIC18 devices with on-chip Ethernet controller.

by Isaac Marino Bavaresco

This is file "coredump.asm".

;===============================================================================
;
; Copyright (c) 2008-2010, Isaac Marino Bavaresco
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;     * Redistributions of source code must retain the above copyright
;       notice, this list of conditions and the following disclaimer.
;     * Neither the name of the author nor the
;       names of its contributors may be used to endorse or promote products
;       derived from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE AUTHOR ''AS IS'' AND ANY
; EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;===============================================================================
; isaacbavaresco@yahoo.com.br
;===============================================================================
                radix   decimal
;===============================================================================
#include <P18CXXX.inc>
;===============================================================================
                code
;===============================================================================
                extern  _startup
;===============================================================================
#define TEST_BOR
;===============================================================================
                global  __init0
                ;---------------------------------------------------------------
                ; Test the reason for the reset without affecting any SFRs or RAM

__init0:        btfss   RCON,5,ACCESS           ; NOT_CM
                bra     CoreDump
                btfss   RCON,NOT_TO,ACCESS      ; NOT_TO
                bra     CoreDump
                btfsc   STKPTR,STKFUL,ACCESS    ; STKFUL
                bra     CoreDump

#ifdef  TEST_BOR
                btfsc   STKPTR,STKUNF,ACCESS    ; STKUNF
                bra     CoreDump
                btfss   RCON,NOT_POR,ACCESS     ; NOT_POR
                bra     Finish
                btfsc   RCON,NOT_BOR,ACCESS     ; NOT_BOR
                bra     Finish
#else
                btfss   STKPTR,STKUNF,ACCESS    ; STKUNF
                bra     Finish
#endif
                ;---------------------------------------------------------------
                ; Save the critical SFRs

CoreDump:       movff   STATUS,EDATA
                movff   WREG,EDATA
                movff   FSR0L,EDATA
                movff   FSR0H,EDATA
                movff   RCON,EDATA
                movff   STKPTR,EDATA

                ;clrwdt

                ;---------------------------------------------------------------
                ; Save the hardware stack

StackDump:      movlw   31
                movwf   FSR0L,ACCESS
                iorwf   STKPTR,f,ACCESS

StackLoop:      movff   TOSL,EDATA
                movff   TOSH,EDATA
                movff   TOSU,EDATA

                decf    STKPTR,f,ACCESS
                decfsz  FSR0L,f,ACCESS
                bra     StackLoop

                ;---------------------------------------------------------------
                ; Save the RAM from 0x000 to 0xeff

RAMDump:        lfsr    0,0

                movlw   0x0f

Loop1:          movff   POSTINC0,EDATA
                cpfseq  FSR0H,ACCESS
                bra     Loop1

                ;---------------------------------------------------------------
                ; Save the RAM from 0xf00 to 0xf5f and the SFR at 0xf60 (EIR)

                movlw   0x61

Loop2:          movff   POSTINC0,EDATA
                cpfseq  FSR0L,ACCESS
                bra     Loop2

                ;---------------------------------------------------------------
                ; Skip the SFR at 0xf61 (EDATA)

                addfsr  0,1
                clrf    EDATA,ACCESS

                ;---------------------------------------------------------------
                ; Save the SFRs from 0xf62 up to 0xfd7

                movlw   0xd8

Loop3:          movff   POSTINC0,EDATA
                cpfseq  FSR0L,ACCESS
                bra     Loop3

                ;---------------------------------------------------------------
                ; Save the SFRs between the INDFx groups

                movlw   3

Loop4:          movff   POSTINC0,EDATA
                movff   POSTINC0,EDATA
                movff   POSTINC0,EDATA

                ; Skip INDFn & family
                addfsr  0,5
                clrf    EDATA,ACCESS
                clrf    EDATA,ACCESS
                clrf    EDATA,ACCESS
                clrf    EDATA,ACCESS
                clrf    EDATA,ACCESS

                decfsz  WREG,f,ACCESS
                bra     Loop4

                ;---------------------------------------------------------------
                ; Save the SFRs from 0xff0 up to 0xfff

                movlw   0x00

Loop5:          movff   POSTINC0,EDATA
                cpfseq  FSR0L,ACCESS
                bra     Loop5

                ;---------------------------------------------------------------
                ; Continue with the boot-up

Finish:         goto    _startup
;===============================================================================
                end
;===============================================================================