Open Collector

Q is the value in the internal register corresponding to the output pin. Usual CMOS output: When Q is high, P is off and N is on. When Q is low, P is on and N is off.
(TTL is the same except P is PNP and N is NPN)

Vcc-------+
          |
      ---[ P channel FET
     |    |
Q ---|    +----------Out
     |    |
      ---[ N channel FET
          |
Vss-------+

Vcc-------+ (a pullup resistor between Vcc and Out gives you a logic 1 when
N is off)
          +--------- Out
          |
     Q ---[ N channel fet
          |
Vss-------+

This configuration is often used in what is called 'wired OR'. Any number of open-drain devices can sit on the same bus, with an external pull-up resistor. The un-asserted state is high (negative logic). Any one of the devices on the bus can pull the signal low to its asserted state, hence creating an OR function on the bus.

The open-collector is often used on interrupt lines. A number of devices sit on the one interrupt signal, and any one of the devices can assert the signal by driving it low. You can add and remove devices from the bus as necessary. This wouldn't be possible with normal logic outputs, because one device would be driving the bus high while another would be driving it low. But an open drain can't drive a signal high, hence the need for an external pull-up. It can only pull a signal low.

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