ON 20040508@8:14:56 AM at page:
http://www.piclist.com/techref/logic/xtrapins.htm#38115.0272337963
James Newton[JMN-EFP-786] published post 38115.0272337963
mfb@pobox.sk
> stops gate voltages rising faster than any internal supply rails for any devices that can latch-up
Pull-up or pull-down resistors ARE useful for bus and signal integrity, but should have NO EFFECT on the parasitic current when tied to one of the supply rails directly with low inductance connection. (Like a common ground plane)
> and so prevent an occasional failure due to bond wires melting.
Bond wires DO NOT MELT. I have tried it, the bonding wire (10um, golden) can withstand 0.5A for short time without being interrupted. What usually fails is the silicon, either there is a oxide breakdown or some PN junction is destroyed by high voltage. (All diodes have a maximum reverse voltage, when this is crossed the junction can be irreversibly damaged). So you can destroy functional I/O pin by just 2mA. (Well that happened to me with no latch-up)
>Latch-up is a danger in chips that have parasitic thyristors as an artifact of the manufacturing process.
All CMOS devices do.
>Most modern chips do not have this problem but its best to be safe.
Not true. ALL CMOS devices contain a parasitic thyristor structure. I have not checked the SOI devices (some high-tech processors like 64-bit IBMs) if they are less sensitive. Only energy required to cause the chip to latch up (parasitic current) varies between the chips and also the current that the device will sink during a latch-up condition. Sone FLASH memories have latch-up current of 150mA max., some PIC devices of about 1A @3.4V saturation voltage which will damage the chip. Military processors can withstand 0.5A for a second into any I/O pin without triggering the parasitic thyristor (SCR for dummies), but at the cost of increased chip size and price.
Mario
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